If you wish to download a full, up-to-date copy of my resume, it can be found here.

ForwardEdge ASIC St. Paul, Minnesota
ASIC Design Verification Engineer | January 2025 - Present
After graduating, I joined ForwardEdge ASIC in a full-time pre-silicon verification role.

Infineon Technologies IR HiRel Andover, Massachusetts
IC Verification Intern | May 2024 - August 2024
My summer internship with Infineon introduced me to analog verification. Referencing the IC verification plan, I utilized Cadence Virtuoso to create top-level testbench schematics with the appropriate variables that would allow me to test the verification objective. I also had to collaborate closely with other verification engineers on the team to ensure consistency across various testbench parameters (process corners, temperatures, supply voltages, etc.) and test methodology. This was critical for obtaining accurate data during regression runs, which in turn was essential for discovering and fixing design issues that could introduce project delays. Following that project, I moved over to the digital environment to overhaul verification infrastructure for the error correction (SECDED) block, designing a parameterized SystemVerilog testbench and set of helper utilities that allowed for quick and effective testing of potential changes to the IP. I was also able to utilize my knowledge of error correction to make significant improvements to the existing SECDED validation framework in preparation for samples of the latest tapeout.

Western Digital Rochester, Minnesota
HDD SoC Development Engineer Intern | May 2023 - August 2023
This was my second experience at Western Digital, returning to the CPU team for the summer of 2023. Again, my primary responsibilities were targeted at creating and debugging UVM testbench components to verify design features, and as such, I continued to hone my knowledge of SystemVerilog and UVM. During my 3-month stint, I was focused primarily on the CPU DRAM datapath, as there were several new hardware features for the latest SoC revision that needed to be verified. This time around, I was much more involved in digging deeper into the RTL to find design issues, as I had pre-existing knowledge of the design and how it worked, and also because I was able to apply waveform analysis skills I'd learned in my processor architecture class in the spring. As a side effect of working on the CPU DRAM datapath, I also learned about CPU memory virtualization and some of its workings and benefits from both a hardware implementation and a software architecture perspective. In addition to these new experiences, I also maintained a few items I had developed during my previous co-op, and continued to collaborate with verification engineers to write effective functional coverage and close out testbench milestones.
HDD SoC Development Engineer Co-Op | May 2022 - December 2022
During my first experience working at Western Digital, I was able to greatly strengthen my understanding of SystemVerilog. In addition, I gained knowledge on a number of critical subjects, including Universal Verification Methodology (UVM), ARM AMBA protocols, and improved my comprehension of object-oriented concepts. Among some other projects, I mainly created and debugged SV/UVM testbench components that allowed further verification of the current SoC revision. I developed system arbitration UVM performance tests that allowed for extraction and analysis of performance and latency data for various CPU datapaths, and applied knowledge of AMBA protocols to create UVM scoreboard setups for several other design components. I also developed a unit-simulation for a critical piece of DRAM datapath IP, which involved creating a SystemVerilog testbench for the IP, as well as an accompanying suite of tests to hit corner-cases not generally seen in the top-level environment. In addition, I wrote functional and code coverage in order to close on testbench milestones, and I worked with a subset of the testbench that allowed for firmware-like C-code to be loaded and tested on the design. As a whole, my first experience working at Western Digital significantly improved my understanding of CPU subsystems on embedded hardware.

Iowa State University Ames, Iowa
Level 1 IT Support | August 2020 - May 2022, January 2023 - December 2024
As IT support for the LAS College, technicians are expected to utilize an enthusiastic, yet professional personality in order to provide a positive experience for professors and students. We deployed and provided support for classroom and office equipment located within our building, as well as remote and on-site support for software and hardware issues via the Service-Now ticket system.

Iowa State University
B.S. Computer Engineering | Completed Decemeber 2024
I graduated Magna Cum Laude with a final GPA of 3.87. I was on the College of Engineering Dean's List during every semester I was enrolled full-time: Fall 2020, Spring/Fall 2021, Spring 2022, Spring/Fall 2023, Spring/Fall 2024.

Woodstock North High School
Graduated with Honors Spring 2020
Academic Challenge Team and VEX Robotics member, McHenry County Honor Band participant, and Varsity Band Section Leader

Cyclone Racing Formula SAE Team, Powertrain | August 2021 - May 2024
The Cyclone Racing Formula SAE Team is a student-run organization whose goal is to create a Formula-style race car that can be entered into yearly competitions held by SAE International. Members must closely adhere to the guidelines set by the team’s technical director, as well as the regulations imposed by Formula SAE’s organizers in order to design a car that is competition-legal (Left: CR-26, Right: CR-27).

FSAE Lead Tuning and Systems Engineer | May 2022 - May 2024
For the 2022 and 2023 school year, I was elected to lead the development of the vehicle systems and tuning aspects of the car. This role involved designing and maintaining a complete electrical system for the car, including charging, power distribution, and wiring. I was also responsible for performing engine calibration, which relied on data analysis to ensure that we were extracting maximum power from the engine while remaining within safe operating limits. Being a part of this team provided me with valuable exposure to engineering principles, and experience working in a fast-paced collaborative environment.

Freshmen Leaders in Engineering | August 2020 - April 2021
ISU Freshmen Leaders in Engineering is an organization that aims to serve as a method of outreach to current and incoming freshmen regarding events and involvement at Iowa State. While we were very restricted in terms of activites as a result of the COVID pandemic, during my time as a member of this group, we planned and executed a fundraiser for the ISU food pantry, and also utilized 360-degree video capture technology to create orientation videos for prospective international students.

WNHS ACES Academic Team | January 2018 - May 2020
I was involved in my high school’s engineering and science academics team from my sophomore year to the end of my senior year. Every member was responsible for studying two subjects that they would subsequently be tested on across several competitions later in the year. We placed first as a team at the regional event in 2019 and 2020, and placed second at the sectional event in 2019. As an individual, I placed first in the subject of engineering graphics at the 2019 regional event, and came third in the same in 2018 and 2020.

WNHS Band Section Leader | August 2019 - May 2020
As trumpet section leader in my high school’s top band, I was responsible for acquainting newcomers with the marching band program, as well as planning some of the choreography for the fall 2019 season. I also collaborated with other section leaders to coordinate activities and build relationships between all members of the band.