4th-year Computer Engineering major with digital design and verification experience at Infineon Technologies and Western Digital
Hi, I’m Anthony Manschula. I’m currently a 4th-year undergraduate student studying Computer Engineering at Iowa State University, with a focus on digital design and verification. I have completed two internships with Western Digital, working as a digital verification engineer on the processor team, and one at Infineon Technologies, doing a mix of analog and digital verification and some digital design. When classes are in session, I work as an IT technician supporting the College of Liberal Arts and Sciences.
Through my classes and work experience, I have knowledge of SystemVerilog and VHDL, UVM, and ARM AMBA protocols. I have worked closely with verification environments incorporating ARM Cortex R8 and M0+ CPUs, and collaborated with team leads to write functional and code coverage in order to close testbench milestones. In addition, I have experience with Cadence tools in both a digital and analog context, from debugging and fixing RTL design issues to creating and simulating pure analog testbenches. I am also familiar with other object-oriented languages, such as Java and C++.
I have had the opportunity for leadership both in high school, as section leader in the band, and at ISU, with my involvement in the Formula SAE team, as well as Freshmen Leaders in Engineering. All of these experiences have allowed me to leverage my communication skills, and pushed my development as a person.
Post-graduation, my goal is to pursue a position that will allow me to continue to utilize and build upon my digital design and verification skills.
If you wish to download a full, up-to-date copy of my resume, it can be found here.
Infineon Technologies IR HiRel Andover, Massachusetts
IC Verification Intern | May 2024 - August 2024
My summer internship with Infineon introduced me to analog verification. Referencing the IC verification plan, I utilized Cadence Virtuoso to create top-level testbench schematics with the appropriate variables that would allow me to test the verification objective. I also had to collaborate closely with other verification engineers on the team to ensure consistency across various testbench parameters (process corners, temperatures, supply voltages, etc.) and test methodology. This was critical for obtaining accurate data during regression runs, which in turn was essential for discovering and fixing design issues that could introduce project delays. Following that project, I moved over to the digital environment to overhaul verification infrastructure for the error correction (SECDED) block, designing a parameterized SystemVerilog testbench and set of helper utilities that allowed for quick and effective testing of potential changes to the IP. I was also able to utilize my knowledge of error correction to make significant improvements to the existing SECDED validation framework in preparation for samples of the latest tapeout.
Western Digital Rochester, Minnesota
HDD SoC Development Engineer Intern | May 2023 - August 2023
This was my second experience at Western Digital, returning to the CPU team for the summer of 2023. Again, my primary responsibilities were targeted at creating and debugging UVM testbench components to verify design features, and as such, I continued to hone my knowledge of SystemVerilog and UVM.
During my 3-month stint, I was focused primarily on the CPU DRAM datapath, as there were several new hardware features for the latest SoC revision that needed to be verified.
This time around, I was much more involved in digging deeper into the RTL to find design issues, as I had pre-existing knowledge of the design and how it worked, and also because I was able to apply waveform analysis skills I'd learned in my processor architecture class in the spring.
As a side effect of working on the CPU DRAM datapath, I also learned about CPU memory virtualization and some of its workings and benefits from both a hardware implementation and a software architecture perspective.
In addition to these new experiences, I also maintained a few items I had developed during my previous co-op, and continued to collaborate with verification engineers to write effective functional coverage and close out testbench milestones.
HDD SoC Development Engineer Co-Op | May 2022 - December 2022
During my first experience working at Western Digital, I was able to greatly strengthen my understanding of SystemVerilog. In addition, I gained knowledge on a number of critical subjects,
including Universal Verification Methodology (UVM), ARM AMBA protocols, and improved my comprehension of object-oriented concepts. Among some other projects, I mainly created and debugged SV/UVM testbench components that allowed further
verification of the current SoC revision. I developed system arbitration UVM performance tests that allowed for extraction and analysis of performance and latency data for various CPU datapaths, and applied knowledge of AMBA protocols
to create UVM scoreboard setups for several other design components. I also developed a unit-simulation for a critical piece of DRAM datapath IP, which involved creating a SystemVerilog testbench for the IP, as well as an accompanying suite
of tests to hit corner-cases not generally seen in the top-level environment. In addition, I wrote functional and code coverage in order to close on testbench milestones, and I worked with a subset of the testbench that allowed for firmware-like C-code to be loaded and tested on the design.
As a whole, my first experience working at Western Digital significantly improved my understanding of CPU subsystems on embedded hardware.
Iowa State University Ames, Iowa
Level 1 IT Support | August 2020 - May 2022, January 2023 - May 2024
As IT support for the LAS College, technicians are expected to utilize an enthusiastic, yet professional personality in order to
provide a positive experience for professors and students. We deployed and provided support for classroom and office equipment located within our
building, as well as remote and on-site support for software and hardware issues via the Service-Now ticket system.
Iowa State University
B.S. Computer Engineering | Expected Graduation Fall 2024
College of Engineering Dean's List: Fall 2020, Spring/Fall 2021, Spring 2022, Spring/Fall 2023, Spring 2024
Woodstock North High School
Graduated with Honors Spring 2020
Academic Challenge Team and VEX Robotics member, McHenry County Honor Band participant, and Varsity Band Section Leader
Cyclone Racing Formula SAE Team, Powertrain | August 2021 - May 2024
The Cyclone Racing Formula SAE Team is a student-run organization whose goal is to create a Formula-style race car that can be entered into yearly competitions held by SAE International.
Members must closely adhere to the guidelines set by the team’s technical director, as well as the regulations imposed by Formula SAE’s organizers in order to design a car that is competition-legal (Left: CR-26, Right: CR-27).
FSAE Lead Tuning and Systems Engineer | May 2022 - May 2024
For the 2022 and 2023 school year, I was elected to lead the development of the vehicle systems and tuning aspects of the car. This role involved designing and maintaining a complete electrical system for the car, including charging, power distribution,
and wiring. I was also responsible for performing engine calibration, which relied on data analysis to ensure that we were extracting maximum power from the engine while remaining within safe operating limits.
Being a part of this team provided me with valuable exposure to engineering principles, and experience working in a fast-paced collaborative environment.
Freshmen Leaders in Engineering | August 2020 - April 2021
ISU Freshmen Leaders in Engineering is an organization that aims to serve as a method of outreach to current and incoming
freshmen regarding events and involvement at Iowa State. While we were very restricted in terms of activites as a result of the COVID pandemic,
during my time as a member of this group, we planned and executed a fundraiser for the ISU food pantry, and also utilized 360-degree video capture
technology to create orientation videos for prospective international students.
WNHS ACES Academic Team | January 2018 - May 2020
I was involved in my high school’s engineering and science academics team from my sophomore year to the end of my senior year. Every member was responsible for studying two
subjects that they would subsequently be tested on across several competitions later in the year. We placed first as a team at the regional event in
2019 and 2020, and placed second at the sectional event in 2019. As an individual, I placed first in the subject of engineering graphics at the 2019
regional event, and came third in the same in 2018 and 2020.
WNHS Band Section Leader | August 2019 - May 2020
As trumpet section leader in my high school’s top band, I was responsible for acquainting newcomers with the marching band program, as well as
planning some of the choreography for the fall 2019 season. I also collaborated with other section leaders to coordinate activities and build
relationships between all members of the band.
January 2024 - December 2024
January 2023 - May 2023
August 2022 - May 2023
January 2024 - December 2024
Iowa State CPRE senior design project, with Boeing as the client.
The aviation industry is adopting multicore systems to handle the demands of modern aviation technology. However, these systems can face interference issues that affect their performance, including the worst-case execution time for safety-critical tasks. To ensure the safety of avionics software, it’s essential to examine and verify how interference impacts these systems. To address this, hardware and software providers are offering advanced partitioning technologies, allowing developers to allocate system resources effectively and minimize interference between applications running on separate processor cores. This project targets a specific ARM-based system-on-chip running the Xen hypervisor using both existing and custom-designed open-source tools to simulate interference scenarios provided by Boeing, aiming to enhance the robustness of avionics software on multicore architectures.
In this project, I have primarily acted as a project coordinator between the group and our contacts at Boeing, and contributed my knowledge of computer architecture to the selection of hardware and development of interference testing programs. As this project focuses heavily on our contribution to and usage of open-source software, a majority of the team’s knowledge base was formed from the Xen Project Wiki as well as exploration of various GitHub repositories relating to system stress and resource management.
A more in-depth project description, along with deliverables and up-to-date weekly progress reports can be found on our senior design website.
January 2023 - May 2023
CPRE 381: Computer Organization and Assembly Level Programming. This project as a whole spanned several months, from February until the end of the semester, with the overall goal of designing several processors around the MIPS ISA with the final goal of comparing their performance. It relied heavily on applying concepts from class, including VHDL skills, piplining, hazard avoidance, and general knowledge of digital logic and the MIPS ISA. This project was completed in a team of two, with both members utilizing Git for version control. Due my partner’s high workload that semester, I was primarily responsbile for the top-level design and integration of the processor, as well as unit testing as features were added. All designs included in the below repository implement the core MIPS ISA, and will run an arbitrary MIPS assembly program (examples included). This project greatly enhanced my understanding of the process of debugging and fixing design issues, which I was introduced to in my first co-op at Western Digital the months prior. This project also familiarized me with the concept of design synthesis, and how different design strategies impact the critical path, and therefore the maximum theoretical clock speed of the processor.
The GitHub repository with the code for the project can be found here.
August 2022 - May 2023
Cyclone Racing Formula SAE Team. This car was designed and built for the 2023 Formula SAE North America competition. As this was my first year being the lead engineer for vehicle systems and tuning, it was quite a learning experience. While I was able to leverage some existing skills from the CR-26 car, considerable thought and planning was necessary to integrate all of the components in my system together in an effective and logical manner. This car required me to improve my knowledge of CAD programs including SolidWorks and AutoCad in order to claim space for my parts in our 3D model, as well as create a wiring diagram to assist us in wiring the car.
There were also several large changes to part selection, including an AiM Motorsports power distribution module, as well as a radically different air intake plenum. While the AiM PDM came with a learning curve and was a costly investment for the team, it proved invaluable by reducing wiring complexity from our previous mechanical fuse and relay block design, as well as providing current draw and output diagnostics for components such as water pumps and fans. The changes to the intake plenum design, while allowing for higher peak horsepower output, proved challenging during fuel map calibration due to the angle of the fuel injectors in relation to the intake runners. As some of the more complex aspects of tuning an engine were beyond my skill range at the time, I reached out to other Formula SAE teams, as well as local engine tuners in Ames for advice on dialing in settings.
The best way to reach me is via email. I monitor this account on most of my devices so expect a reasonably quick response. Alternatively, you can reach me via a message on LinkedIn.
My email address: