Hi, I’m Anthony

4th-year Computer Engineering major with experience as an SoC Development Engineer at Western Digital

About Me


Hi, I’m Anthony Manschula. I’m currently a 4th-year undergraduate student studying Computer Engineering at Iowa State University, with a focus on computer architecture and digital design. I have interned twice at Western Digital, where I was as a part of the HDD CPU team. When classes are in session, I work as an IT Technician supporting the College of Liberal Arts and Sciences, and I also participate in the Formula SAE team we have on campus.

Through my classes and work experience, I have knowledge of Verilog/SystemVerilog hardware description languages, UVM, and ARM AMBA protocols. I have worked closely with verification environments incorporating ARM Cortex R8 and M0+ CPUs, and collaborated with team leads to write functional and code coverage in order to close testbench milestones. In addition, I have experience with using Cadence Xcelium Waveform Analysis tools to debug and fix RTL design issues discovered as a result of my verification. I am also familiar with other object-oriented languages, such as Java.

I have had the opportunity for leadership both in high school, as section leader in the band, and at ISU, with my involvement in the Formula SAE team, as well as Freshmen Leaders in Engineering. All of these experiences have allowed me to leverage my communication skills, and pushed my development as a person.

Post-graduation, my goal is to pursue employment in a field that will allow me to leverage and continue to build upon my computer architecture and design skills.


If you wish to download a full, up-to-date copy of my resume, it can be found here.

Western Digital Rochester, Minnesota
HDD SoC Development Engineer Intern | May 2023 - August 2023
This was my second experience at Western Digital, returning to the CPU team for the summer of 2023. Again, my primary responsibilites were targeted at creating and debugging UVM testbench components to verify design features, and as such, I continued to hone my knowledge of SystemVerilog and UVM. During my 3-month stint, I was focused primarily on the CPU DRAM datapath, as there were several new hardware features for the latest SoC revision that needed to be verified. This time around, I was much more involved in digging deeper into the RTL to find design issues, as I had pre-existing knowledge of the design and how it worked, and also because I was able to apply waveform analysis skills I'd learned in my processor architecture class in the spring. As a side effect of working on the CPU DRAM datapath, I also learned about CPU memory virtualization and some of its workings and benefits from both a hardware implementation and a software architecture perspective. In addition to these new experiences, I also maintained a few items I had developed during my previous co-op, and continued to collaborate with verification engineers to write effective functional coverage and close out testbench milestones.
HDD SoC Development Engineer Co-Op | May 2022 - December 2022
During my first experience working at Western Digital, I was able to greatly strengthen my understanding of SystemVerilog. In addition, I gained knowledge on a number of critical subjects, including Universal Verification Methodology (UVM), ARM AMBA protocols, and improved my comprehension of object-oriented concepts. Among some other projects, I mainly created and debugged SV/UVM testbench components that allowed further verification of the current SoC revision. I developed system arbitration UVM performance tests that allowed for extraction and analysis of performance and latency data for various CPU datapaths, and applied knowledge of AMBA protocols to create UVM scoreboard setups for several other design components. I also developed a unit-simulation for a critical piece of DRAM datapath IP, which involved creating a SystemVerilog testbench for the IP, as well as an accompanying suite of tests to hit corner-cases not generally seen in the top-level environment. In addition, I wrote functional and code coverage in order to close on testbench milestones, and I worked with a subset of the testbench that allowed for firmware-like C-code to be loaded and tested on the design. As a whole, my first experience working at Western Digital significantly improved my understanding of CPU subsystems on embedded hardware.

Iowa State University Ames, Iowa
Level 1 IT Support | August 2020 - May 2022, January 2023 - May 2023
As IT support for the LAS College, technicians are expected to utilize an enthusiastic, yet professional personality in order to provide a positive experience for professors and students. We deployed and provided support for classroom and office equipment located within our building, as well as remote and on-site support for software and hardware issues via the Service-Now ticket system.

The Home Depot McHenry, Illinois
Sales Associate | May 2021 - August 2021
Sales Associates at The Home Depot leverage store and product knowledge, a helpful disposition, and effective communication skills to satisfy customers' needs and drive sales.


Iowa State University
B.S. Computer Engineering | Expected Graduation Fall 2024
College of Engineering Dean's List: Fall 2020, Spring/Fall 2021, Spring 2022, Spring/Fall 2023

Woodstock North High School
Graduated with Honors Spring 2020
Academic Challenge Team and VEX Robotics member, McHenry County Honor Band participant, and Varsity Band Section Leader

Activities & Involvement

Cyclone Racing Formula SAE Team, Powertrain | August 2021 - Present
The Cyclone Racing Formula SAE Team is a student-run organization whose goal is to create a Formula-style race car that can be entered into yearly competitions held by SAE International. Members must closely adhere to the guidelines set by the team’s technical director, as well as the regulations imposed by Formula SAE’s organizers in order to design a car that is competition-legal (Left: CR-26, Right: CR-27).

FSAE Lead Tuning and Systems Engineer | May 2022 - Present
For the 2022 and 2023 school year, I was elected to lead the development of the vehicle systems and tuning aspects of the car. This role involves designing and maintaining a complete electrical system for the car, including charging, power distribution, and wiring. I am also responsible for performing engine calibration, which relies on data analysis to ensure that we are extracting maximum power from the engine while remaining within safe operating limits. Being a part of this team has provided me with valuable exposure to engineering principles, and experience working in a fast-paced collaborative environment.

Freshmen Leaders in Engineering | August 2020 - April 2021
ISU Freshmen Leaders in Engineering is an organization that aims to serve as a method of outreach to current and incoming freshmen regarding events and involvement at Iowa State. While we were very restricted in terms of activites as a result of the COVID pandemic, during my time as a member of this group, we planned and executed a fundraiser for the ISU food pantry, and also utilized 360-degree video capture technology to create orientation videos for prospective international students.

WNHS ACES Academic Team | January 2018 - May 2020
I was involved in my high school’s engineering and science academics team from my sophomore year to the end of my senior year. Every member was responsible for studying two subjects that they would subsequently be tested on across several competitions later in the year. We placed first as a team at the regional event in 2019 and 2020, and placed second at the sectional event in 2019. As an individual, I placed first in the subject of engineering graphics at the 2019 regional event, and came third in the same in 2018 and 2020.

WNHS Band Section Leader | August 2019 - May 2020
As trumpet section leader in my high school’s top band, I was responsible for acquainting newcomers with the marching band program, as well as planning some of the choreography for the fall 2019 season. I also collaborated with other section leaders to coordinate activities and build relationships between all members of the band.


Multicore Operational Analysis Tooling

January 2024 - December 2024

CPRE 381: VHDL Processor Design

January 2023 - May 2023

Cyclone Racing CR-27

August 2022 - May 2023


The best way to reach me is via email. I monitor this account on most of my devices so expect a reasonably quick response. Alternatively, you can reach me via a message on LinkedIn.

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